In recent years, a semiconductor recording device such as a SD (Secure Digital) card that is a card-type recording medium incorporating a flash memory has been extremely-compact and extremely-thin, has been able to be easily handled, and accordingly has been widely used for recording data such as an image in a digital camera and portable apparatus.
The flash memory incorporated in the semiconductor recording device is composed of many physical blocks of a constant size, and is a memory able to erase data in units of physical block. To satisfy a recent request for enlargement of the capacity, a multi-level flash memory able to accumulate two bits or more in one cell is commercialized as the flash memory.
FIG. 1 shows an example of a relationship between the number of electrons accumulated in a floating gate of the multi-level flash memory and a threshold voltage (Vth). As shown in FIG. 1, in a four-valued flash memory, an accumulation state of the electrons in the floating gate is managed in four states in accordance with the threshold voltage (Vth). In an erased state, an electric potential is in a lowest level, which is shown as (1, 1). Then, as the electrons are accumulated, the threshold voltage discretely increases, and the states are shown as (1, 0), (0, 0), and (0, 1). In this manner, since the electric potential rises in proportion to the number of accumulated electrons, the recording of 2-bit data in one cell can be realized by controlling the electric potential so as to be within a predetermined threshold value.
FIG. 2 shows a schematic diagram of one physical block of the four-valued flash memory. The physical block shown in FIG. 2 is composed of 2*K pages (K is a natural number). And, a writing process is carried out in ascending order from page number 0. Here, it is assumed that a page of page number m (0<=m<K) and a page of page number (K+m) are in a relation of sharing one memory (hereinafter referred to as a cell sharing relation). In the pages being in the cell sharing relation, a firstly written page is referred to as a first page, and a subsequently written page is referred to as a second page. That is, the writing to the page number m (the writing to the first page) and the writing to the page number (K+m) (the writing to the second page) are the charging of electrons to a same cell. Explained referring to FIG. 1, in the writing to the first page, the electric potential is controlled so as to rise to a half level, and in the next writing to the second writing, the electric potential is controlled so as to rise to a maximum level. FIG. 3 shows a state transition of the flash memory cell. As shown in FIG. 3, the state of one memory cell of the physical block of the flash memory transits as follows.                (a) After erasing data, the state of memory cell is (1, 1).        (b) After the writing to the first page, the state of cell is (1, 1) or (1, 0).        (c) After the writing to the second page, the state of cell is (1, 1), (1, 0), (0, 0), or (0, 1).        
As mentioned above, in the multi-level flash memory, a multi-level recording that provides a plurality of threshold values to Vth and controls an accumulation amount of electrons in the flash memory is carried out, and thereby realizing the enlargement of capacity.
The abovementioned states (b) and (c) will be explained in detail more. In (b), a state after writing “1” to a memory cell of the first page is (1, 1), and a state after writing “0” is (1, 0). Additionally, in (c), the transition is restricted depending on the state in (b). Specifically, the transition from the state of (1, 1) in (b) will be retained in the state of (1, 1) in the case of writing “1”, and will be in (0, 1) in the case of writing “0”. Meanwhile, the transition from the state of (1, 0) in (b) will be retained in the state of (1, 0) in the case of writing “1”, and will be in (0, 0) in the case of writing “0”.
However, in a process of the transition from (b) to (c), a problem that a writing error propagates to the already written first page will occur. That is, in carrying out the electron injection to set the memory cell being in (1, 1) in (b) to the state of (0, 1), the electric potential sometimes does not rise to the Vth corresponding to (0, 1) due to a life expiration of the cell to stop in midstream. When stopping at (1, 0) for example, the already written first page transits from “1” to “0”. In this case, there has been not only the error of the second page but also a problem that the error propagates to the first page.
The writing of page 0 to page (K−1) shown in FIG. 2 is the writing to the first page, and the writing error of this case is the error where the Vth does not rise to (1, 0) from the state of (1, 1). In addition, the writing of page K to page (2K−1) shown in FIG. 2 is the writing to the second page, and the state of the Vth becomes (1, 1), (1, 0), (0, 0), and (0, 1). The writing error on this case includes the following two errors.
(Error 1) The Vth (1, 0) does not rise to (0, 0).
(Error 2) The Vth (1, 1) does not rise to (0, 1).
In the case of error 1, the Vth (1, 0) is adjacent to the Vth (0, 0); however, the Vth (1, 1) and the Vth (0, 1) of the case of error 2 sandwich two states therebetween. In particular, the Vth (1, 0) is a value after the writing of the first page, and in a case where the Vth does not rise to over (1, 0) in the writing of the second page, not only the second page causes a writing error, but also data of the first page is destructed as a result. For example, the writing error that occurred in the writing of page K may destruct data already written to page 0.
To solve the problem, Patent document 1 includes a buffer memory in a memory controller for controlling the flash memory, stores data of the first page in the buffer memory until the writing of the second page completes, and in a case where a writing error has occurred in the writing of the second page, controls so as to load the data of the buffer memory and to also write the data of the first page to the flash memory again.    Patent document 1: Japanese Unexamined Patent Publication No. 2006-318366